As shown in FIG. 1, a constant on time switching DC-DC power supply employs a control circuit 10 to provide a control signal Sd to control an output stage 11 to generate a regulated output voltage Vout. The output stage 11 includes a pair of power switches M1 and M2 connected in series, an inductor L and a capacitor C in the manner that the inductor L is connected between the switching node between the power switches M1 and M2 and the capacitor C. In the control circuit 10, a feedback circuit 16 detects the output voltage Vout to generate a feedback signal Vfb, an error comparator 14 compares the feedback signal Vfb with a reference voltage Vref to generate a comparison signal EC, and a control logic circuit 12 triggers the on time of the control signal Sd according to the comparison signal EC. The control logic circuit 12 includes a flip-flop 20 to trigger a signal Vc in response to the comparison signal EC, an on time one shot circuit 18 to trigger a signal Sr according to the signal Vc to reset the flip-flop 20, and a driver 22 to generate the control signal Sd in response to the signal Vc. In the control logic circuit 12, the on time one shot circuit 18 and the flip-flop 20 establish a constant on time trigger for generating the signal Vc that has a constant pulse width for the on time of the control signal Sd. For constant off time switching DC-DC power supply, the constant on time trigger is replaced by a constant off time trigger for generating a constant pulse width for the off time of the control signal for the output stage.
FIG. 2 is a waveform diagram of the switching DC-DC power supply shown in FIG. 1. Referring to FIGS. 1 and 2, when the feedback signal Vfb goes down beyond the reference voltage Vref, as shown at time t1, the comparison signal EC turns to high from low, thereby triggering the signal Vc to turn on the high side power switch M1 to charge the inductor L, and the output voltage Vout acquires energy through the filter composed of the inductor L and the capacitor C. After triggered by the signal Vc, the signal Sr lasts for a constant pulse width time and then terminates to reset the flip-flop 20 to turn off the signal Vc, as shown at time t2, thereby turning on the low side power switch M2 to release the energy of the inductor L. This energy release continues until the feedback signal Vfb goes down beyond the reference voltage Vref again, and then the process enters the next cycle. This is a complete cycle of a constant on time control system.
As compared with the other pulse width modulation (PWM) control circuits, the constant on time control circuit 10 uses the error comparator 14 instead of an error amplifier, thereby advantageously having simpler circuit, requiring no compensation circuit and allowing fast response. Yet, its defect is that the real output voltage Vout may depart from the design value of the output voltage. As shown in FIG. 3, the real output voltage Vout has the waveform 24 and the average Vout(dc) 26 that departs from its design value Vout(set) 28 due to the combined influence of the output ripple Vripple, the offset Voff of the error comparator 14 itself, the response delay Td and the output voltage, output inductance and capacitance of the applied circuit. To solve this problem, conventionally, the offset Voff of the error comparator 14 is adjusted, for example, by adding or subtracting a fixed value to or from the offset Voff of the error comparator 14. However, the output ripple Vripple, the offset Voff and the response delay Td usually vary with the input voltage, output voltage, output inductance, output capacitance, and the slew rate of the input terminal of the applied circuit, causing it difficult to provide adjustment adaptable to all conditions.
Therefore, it is desired a control circuit and method to dynamically adjust the offset of an error comparator of a switching DC-DC power supply depending on real application environments.